Lab Sheet 4#

This lab sheet contains the following lab activities:

Lab 1: PWM Signal Generation with Push Buttons#

Learn how to write VHDL code to generate a PWM signal with an adjustable duty cycle.
Learn how to debounce input signals from push buttons and detect button clicks.

Write VHDL code that implements a single-channel PWM generator (duty cycle adjustable with push buttons). The design has the following I/Os.
- RST_N Asynchronous active-low reset (input)
- CLK 50MHz system clock (input)
- FSEL PWM frequency select (input)
- UP PWM duty cycle increment (input)
- DOWN PWM duty cycle decrement (input)
- PWM PWM (output)
The PWM frequency is selectable: 1kHz (FSEL=0) or 10kHz (FSEL=1). To select the PWM frequency, use a slide switch on the FPGA board.
The PWM signal has 8-bit resolution for the duty cycle.
To change the PWM duty cycle (in the range between 0% and 100%), use two push buttons (UP and DOWN) on the FPGA board.
- Every time the UP or DOWN button is pressed and released, the PWM duty is incremented or decremented by 5%, respectively.
- For the UP and DOWN push buttons, debouncing logic should be implemented.
Write a VHDL testbench and simulate the VHDL code using a VHDL simulator to verify your design. Capture the simulation waveforms for different frequency and duty cycle values.
Test the design on the MAX10 Lite board. Specify the FPGA pin assignments properly for your design.
Measure the PWM output signal with a digital oscilloscope. Capture the waveforms for different frequency and duty cycle values.
Demonstrate your FPGA design to the lab instructor.

Learn how to write VHDL code to generate a PWM signal with an adjustable duty cycle.
Learn how to detect the rotation direction and changes on the input signals from a rotary encoder module.

Write VHDL code for a single-channel PWM generator similar to Lab 1, but use a rotary encoder switch module to increment and decrement the PWM duty cycle.
The design has the following I/Os.
- RST_N Asynchronous active-low reset (input)
- CLK 50MHz system clock (input)
- FSEL PWM frequency select (input): 0=1kHz, 1=10kHz
- A Rotary encoder channel A (input)
- B Rotary encoder channel B (input)
- SW Rotary encoder switch (input)
- PWM PWM (output)
The PWM duty cycle is increased or decreased by rotating the knob of the rotary encoder switch module, clockwise or counter-clockwise, respectively.
If the switch of the module is clicked, the duty cycle is set to 0%.
Test the design on the MAX10 Lite board. Specify the FPGA pin assignments properly for your design.
Measure the PWM output signal with a digital oscilloscope. Capture the waveforms for different frequency and duty cycle values.
Demonstrate your FPGA design to the lab instructor.

Learn how to write VHDL code to generate multiple PWM signals with adjustable duty cycles.
Learn how to debounce input signals from push buttons and detect button clicks.

Write VHDL code that implements an RGB LED driver with PWM-based LED dimming.
The design has the following I/Os.
- RST_N Asynchronous active-low reset (input)
- CLK 50MHz system clock (input)
- PB[2:0] Push buttons (input)
- RGB_PWM[2:0] 3-channel PWM (output)
The three PWM output signals have the same frequency of 500Hz.
To change the duty cycle of each PWM signal, a push button is used.
- When the button associated with a PWM signal is held pressed, the duty cycle is increased by 1% every 100 msec.
- If the duty cycle reaches 100%, it wraps around to 0%.
Write a VHDL testbench and simulate the VHDL code using a VHDL simulator to verify your design. Capture the simulation waveforms for different frequency and duty cycle values.
Test the design with the MAX10 Lite board. Specify the FPGA pin assignments properly for your design.
Measure the PWM output signals with a digital oscilloscope. Capture the waveforms for different duty cycle values.
Demonstrate your FPGA design to the lab instructor.

Learn how to write VHDL code to generate multiple PWM signals with adjustable duty cycles.
Learn how to scan the keypad and detect a key sequence.

Write VHDL code for a PWM-based RGB LED driver.
The design has the following I/Os.
- RST_N Asynchronous active-low reset (input)
- CLK 50MHz system clock (input)
- ROWS[3:0] Row lines for keypad (input)
- COLS[3:0] Column lines for keypad (output)
- RGB_LEDS[2:0] PWM signals for RGB (output)
Use a 4x4 membrane keypad and scan the key presses. Key presses are used to set the duty cycle of each PWM output channel.
Use the following keypress sequence to set color values: *RRGGBB#
- The sequence starts with * and ends with #.
- The duty-cycle value for each color is given in decimal 00-99.
- For example: *250050# means R=25%, G=0%, and B=50%.
Test the design with the MAX10 Lite board. Specify the FPGA pin assignments properly for your design.
Demonstrate your design to the lab instructor.

Write VHDL code for a WS2812B-based RGB LED driver.
The design has the following I/Os.
- RST_N Asynchronous active-low reset (input)
- CLK 50MHz system clock (input)
- ROWS[3:0] Row lines for a 4x4 keypad (input)
- COLS[3:0] Column lines for a 4x4 keypad (output)
- WS_DATA Data line for the WS2812B module (output)
Use a 4x4 membrane keypad and scan the key presses.
Use the following keypress sequence to set the color 24-bit value of the WS2812B:
- The sequence starts with * and ends with #.
- *Axxx# for the 8-bit decimal value (0..255) for the Red color
- *Bxxx# for the 8-bit decimal value (0..255) for the Green color
- *Cxxx# for the 8-bit decimal value (0..255) for the Blue color
- For example:*A064# (Red = 64), *B000# (Green = 0), and *C255# (Blue = 255).
Test the design with the MAX10 Lite board. Specify the FPGA pin assignments properly for your design.
Demonstrate your design to the lab instructor.

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Created: 2025-07-11 | Last Updated: 2025-07-11