Lab Sheet 3#

This lab sheet contains the following lab activities:

Hardware / Software Required#

  • Intel DE10-Lite FPGA board (with a USB cable)
  • Computer with USB ports + Intel Quartus Prime Lite + VHDL Simulator
  • Digital Oscilloscope
  • RGB Module

Lab 1: RS Latch#

Objective#

  • Learn how to write synthesizable VHDL code to implement an RS latch targeting an FPGA.

Lab Procedure#

  1. Write VHDL code to implement an RS latch using two cross-coupled two-input NAND gates.

    • Use two onboard slide switches, SW(0) and SW(1), as active-low inputs /S (set) and /R (reset) for the RS latch.
    • The RS latch has two complementary outputs: Q (non-inverting) and QB (inverting), driving two onboard LEDs LEDS(0) and LEDS(1) respectively.

  2. Test the design on the MAX10 Lite FPGA board and measure the output signals using a digital oscilloscope.

    • Make sure that FPGA pin assignments for the I/O signals are applied correctly.

  3. Write the observed logic states of the RS latch for each switch combination using the following truth table.

  4. Reimplement the RS latch using two-input NOR gates instead of two-input NAND gates.

    • Change the inputs of the RS latch to R and S (both active-high).
    • Test the design on the FPGA board to verify its correctness.
SW(0) SW(1) LEDS(0) LEDS(1)
LOW HIGH
HIGH LOW
HIGH HIGH
LOW LOW

Table: Truth Table for RS Latch

Figure: The schematic of a clock divider based on T-FFs, as shown in the RTL Viewer

Post-Lab Questions for Lab 1#

  1. According to the post-mapping report provided by Quartus Prime Lite, how many logic cells of MAX10 FPGA are used to implement the RS Latch?

  2. What happens to the output Q and QB when both inputs R_N and S_N are LOW?

  3. How would replacing the NAND gates with NOR gates change the behavior of the RS latch?

 

Lab 2: D Flip-Flops and Toggle Flip-Flops#

Objective#

  • Learn how to use VHDL to implement a D flip-flop, a toggle flip-flop and a clock divider based on toggle flip-flops.

Lab Procedure#

  1. Write synthesizable VHDL code to implement a D flip-flop (D-FF) using two D latches in a master-slave configuration.

    • Use the VHDL code of a D latch (d_latch) provided below.

  2. Implement a toggle flip-flop (T-FF) based on a D flip-flop implemented in Step 1.

  3. Write VHDL code for a fully synchronous design (toggle_output) that utilizes a chain of T-FFs to generate a toggle output at a frequency lower than the system clock (50MHz).

    • A slide switch SW(0) is used as the toggle input (to enable/disable toggling).
    • The design uses a 50 MHz clock input CLK and produces two complementary output signals: Q and QB.
    • Capture the schematic of the synthesized circuit (with ) in the RTL Viewer for inclusion in the lab report.

  4. Write a VHDL testbench for the toggle_output design.

    • Use a VHDL simulator to simulate the design with the VHDL testbench.
    • Capture the simulation waveforms for inclusion in the lab report.

  5. Test the toggle_output design using the MAX10 Lite FPGA board and measure the output signals using a digital oscilloscope.

    • Use the PIN_AB21 and PIN_AA20 pins (3.3V LVTTL) for outputs Q and QB.
    • Capture the waveforms of the output signal for inclusion in the lab report.
    • Try a different number of T-FFs (change to a larger integer value), recompile and upload to the FPGA board to observe the difference using an oscilloscope.
-- File: d_latch.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY d_latch IS
    PORT (
        D  : IN  STD_LOGIC; -- Data input
        EN : IN  STD_LOGIC; -- Enable input
        Q  : OUT STD_LOGIC; -- Output Q
        QB : OUT STD_LOGIC  -- Inverted output (Q-bar)
    );
END d_latch;

ARCHITECTURE dataflow OF d_latch IS
    SIGNAL q_int : STD_LOGIC := '0';
BEGIN
    -- MUX2_1 logic
    q_int <= D WHEN EN = '1' ELSE q_int;
    -- Concurrent signal assigments for outputs
    Q  <= q_int;
    QB <= NOT q_int;
END dataflow;

 

Post-Lab Questions for Lab 2#

  1. What is the output frequency of the toggle_output design when using ?

  2. For the toggle_output design, what is a possible value for so that the frequency of the output is between 1Hz and 10Hz?

  3. Identify the longest or critical path of the toggle_output design as shown in the RTL Viewer.

 

Lab 3: Shift Register#

Objective#

  • Learn how to use VHDL to implement a shift register.

Lab Procedure#

  1. Write synthesizable VHDL code:

    • The design entity (leds_shift_reg) has the following I/Os:
      • A 50 MHz clock signal as input: CLK_50MHZ
      • A push button used as an active-low asynchronous reset input: RST_N
      • A push button: PB (active-low)
      • 10-bit slide switches as inputs: SW(9..0)
      • 10-bit LEDs as outputs: LEDS(9..0)
    • The PB input should be filtered with a debounce module.
    • If RST_N is held LOW, the circuit enters the reset state and loads the values of the slide switches SW into an internal shift register. However, if the SW inputs are all 0s, the least significant bit (LSB) is set to`'1' and the rest to '0'.
    • If the system reset is de-asserted and there is a rising edge on PB, the shift register performs a circular left shift by one position. Otherwise, the shift register retains its current state.
    • The LEDS display the current value of the shift register.

  2. Write a VHDL testbench to verify the design.

    • Simulate the design using the testbench.
    • Capture the simulation waveforms for inclusion in the lab report.

  3. Test your FPGA design using the DE10-Lite FPGA board:

    • Implement and download your design to the FPGA board.
    • Demonstrate your design to the lab instructor for validation.

 

Lab 4: Up-Down Binary Counter with a Slower Clock#

Objective#

  • Learn how to use VHDL to implement a binary counter in up/down mode.

Lab Procedure#

  1. Write synthesizable VHDL code:

    • The design entity (counter) has the following I/Os:
      • a 50 MHz clock signal as input: CLK_50MHZ
      • a push button used as an active-low asynchronous reset input: RST_N
      • two slide switches: UP_DOWN(1..0)
      • 10-bit LEDs as outputs: LEDS(9..0)
    • If RST_N is held LOW, the circuit enters the reset state and load 0s into the register of an internal 10-bit binary counter.
    • The counter's value is between 0x000 and 0x3FF (hex). The value wraps around in case of an overflow or an underflow.
    • If the system reset is de-asserted:
      • UP_DOWN[1:0] = "01": the counter increments its value by 1 every 100 msec.
      • UP_DOWN[1:0] = "10": the counter decrements its value by 1 every 100 msec.
      • Otherwise, the counter retains its current value.
    • The LEDs display the current value of the binary counter.
    • The top-level design unit (shown in the VHDL code template below) must be composed of two submodules, which are to be implemented in VHDL:
      • a binary counter module (updown_counter)
      • a clock tick generator module (tick_gen), used to generate a periodic clock enable signal for the binary counter module.

  2. Write a VHDL testbench to verify the design.

    • Simulate the design using the testbench.
    • Capture the simulation waveforms for inclusion in the lab report.

  3. Use Quartus Prime Lite to compile source code and upload the bitstream file to the FPGA board for testing purposes.

    • Demonstrate your design to the lab instructor for validation.
-- File: counter.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY counter IS
    PORT (
        CLK_50MHZ : IN STD_LOGIC;
        RST_N     : IN STD_LOGIC;
        UP_DOWN   : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        LEDS      : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
    );
END counter;

ARCHITECTURE structural OF counter IS

    COMPONENT tick_gen IS
        GENERIC (
            BW : INTEGER;
            MAX_VALUE : INTEGER
        );
        PORT (
            CLK   : IN STD_LOGIC; -- clock input
            RST_N : IN STD_LOGIC; -- active-low, asynchronous input
            TICK  : OUT STD_LOGIC -- single-cycle, periodic clock pulse
        );
    END COMPONENT;

    COMPONENT updown_counter IS
        GENERIC ( BW : INTEGER );
        PORT (
            CLK    : IN STD_LOGIC; -- clock input
            RST_N  : IN STD_LOGIC; -- active-low, asynchronous input
            CE     : IN STD_LOGIC; -- clock enable input
            UPDOWN : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- updown control input
            Q      : OUT STD_LOGIC_VECTOR(BW - 1 DOWNTO 0) -- counter output
        );
    END COMPONENT;

    SIGNAL tick : STD_LOGIC;
    SIGNAL counter_out : STD_LOGIC_VECTOR(9 DOWNTO 0);

BEGIN
    -- Instantiate tick generator
    TICK_GEN_inst : ENTITY work.tick_gen
        GENERIC MAP(
            BW => 20,
            MAX_VALUE => 500000 - 1
        )
        PORT MAP(
            CLK   => CLK_50MHZ,
            RST_N => RST_N,
            TICK  => tick
        );

    -- Instantiate up/down counter
    COUNTER_inst : ENTITY work.updown_counter
        GENERIC MAP( BW => 10 )
        PORT MAP(
            CLK    => CLK_50MHZ,
            RST_N  => RST_N,
            CE     => tick,
            UPDOWN => UP_DOWN,
            Q      => counter_out
        );

    LEDS <= counter_out; -- Output to LEDs
END structural;

Figure: The schematic of the up-down counter consisting of a clock tick generator module (tick_gen) and a binary counter module (updown_counter), as shown in the RTL Viewer

 

Lab 5: Bit Sequence Detector#

Objective#

  • Learn how to implement an FSM-based bit sequence detector using VHDL for detecting a specified bit sequence within a 10-bit input loaded from slide switches.

Lab Procedure#

  1. Write VHDL code to implement a bit sequence detector that detects a 5-bit pattern in a 10-bit sequence.

  2. The top-level design (bit_seq_detect_test) has the following I/O interface:

    • CLK: Clock input (50 MHz)
    • RST_N: Asynchronous active-low reset input
    • START: Start input
    • SW(9..0): 10-bit slide switch input
    • LEDS(1..0): 2-bit status LED output

  3. Functional Description

    • Initial State:
      • All LEDs are OFF.
      • System waits for a start triggered by a button click.
    • On START Trigger:
      • The value of SW(9..0) is loaded into an internal shift register.
      • Shifting begins on each rising edge of CLK.
      • Bits are shifted out with the MSB first, and LSB is filled with '0'.
      • During shifting, all LEDs are turned OFF.
    • Detection & Output Logic:
      • The shift register output is monitored by a bit sequence detector.
      • If the target bit pattern is detected, input bit shifting halts, LEDS(1) is turned ON, and the circuit returns to the initial state.
      • If all 10 bits have been shifted and no match is found, the shifting process completes, LEDS(0) is turned ON, and the circuit returns to the initial state.
    • Reset Logic:
      • If RST_N is LOW, the system enters a reset state immediately.

  4. Implementation Guidelines

    • The top-level design must instantiate the bit_seq_detect module, which should be implemented separately using an FSM modeling style.
    • The bit sequence detector has the following I/O interface:
      • CLK 50 MHz clock input
      • RST_N Asynchronous active-low reset input
      • ENA Enable input (high active)
      • DIN Data bit input
      • MATCH Match status output (high active)
    • Functional Description:
      • On every rising edge of CLK, the FSM samples DIN if ENA is HIGH.
      • If ENA is LOW or RST_N is LOW (reset asserted), the FSM returns to the initial state.
      • The FSM starts processing when ENA is HIGH.
      • When the target bit sequence is detected, the output MATCH goes HIGH for one clock cycle. Otherwise, the output is LOW.
    • Target Sequence: 1 0 1 1 0
    • A VHDL testbench is provided as an example for simulating the bit_seq_detect module.
      • Use the VHDL testbench to simulate your bit_seq_detect module.
      • Capture the simulation waveform for inclusion in the lab report.

  5. Create a Quartus Prime Lite project, compile the VHDL source code, and upload the bitstream to the MAX10 Lite board for testing purposes.

    • Capture the schematic in the RTL Viewer and the FSM of the bit_seq_detect circuit shown in State Machine Viewer for inclusion in the lab report.
    • Demonstrate your design to the lab instructor for validation.

VHDL Testbench Code Listing

-- File: tb_bit_seq_detect.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb_bit_seq_detect IS
END tb_bit_seq_detect;

ARCHITECTURE sim OF tb_bit_seq_detect IS
    -- DUT Signals
    SIGNAL t_CLK   : STD_LOGIC := '0';
    SIGNAL t_RST_N : STD_LOGIC := '0';
    SIGNAL t_ENA   : STD_LOGIC := '0';
    SIGNAL t_DIN   : STD_LOGIC := '0';
    SIGNAL t_MATCH : STD_LOGIC;

    -- Clock period
    CONSTANT CLK_PERIOD : TIME := 20 ns; -- 50 MHz

    -- Sequence to test: 1 0 1 1 0 = MATCH
    SIGNAL test_seq : STD_LOGIC_VECTOR(19 DOWNTO 0)
                      := b"0101_1010_1111_0110_0100";

    -- Component declaration
    COMPONENT bit_seq_detect IS
        PORT (
            CLK   : IN STD_LOGIC;
            RST_N : IN STD_LOGIC;
            ENA   : IN STD_LOGIC;
            DIN   : IN STD_LOGIC;
            MATCH : OUT STD_LOGIC
        );
    END COMPONENT;

BEGIN
    -- DUT instance
    uut : ENTITY work.bit_seq_detect
        PORT MAP(
            CLK   => t_CLK,
            RST_N => t_RST_N,
            ENA   => t_ENA,
            DIN   => t_DIN,
            MATCH => t_MATCH
        );

    -- Clock generation
    clk_proc : PROCESS
    BEGIN
        t_CLK <= '0';
        WAIT FOR CLK_PERIOD / 2;
        t_CLK <= '1';
        WAIT FOR CLK_PERIOD / 2;
    END PROCESS;
    t_DIN <= test_seq(test_seq'left);

    -- Stimulus process
    stim_proc : PROCESS
    BEGIN
        -- Initial reset
        t_RST_N <= '0';
        t_ENA <= '0';
        WAIT FOR 200 ns;
        t_RST_N <= '1';
        WAIT UNTIL rising_edge(t_CLK);

        FOR i IN 0 TO test_seq'left LOOP
            IF i >= 2 AND i <= 4 THEN
                t_ENA <= '0';
            ELSE
                t_ENA <= '1';
            END IF;
            test_seq <= test_seq(test_seq'left - 1 DOWNTO 0) & '0';
            WAIT UNTIL rising_edge(t_CLK);
        END LOOP;

        t_ENA <= '0';
        WAIT FOR 5 * CLK_PERIOD;
        REPORT "Simulation finished" SEVERITY note;
        WAIT;
    END PROCESS;

END sim;

VHDL Code Listing: bit_seq_detect_test.vhd

-- File: bit_seq_detect_test.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY bit_seq_detect_test IS
    PORT (
        CLK   : IN STD_LOGIC; -- 50 MHz clock
        RST_N : IN STD_LOGIC; -- Asynchronous active-low reset
        START : IN STD_LOGIC; -- Start trigger input
        SW    : IN STD_LOGIC_VECTOR(9 DOWNTO 0); -- 10-bit slide switch input
        LEDS  : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) -- 2-bit status LED output
    );
END bit_seq_detect_test;

ARCHITECTURE rtl OF bit_seq_detect_test IS

    -- Component declaration
    COMPONENT bit_seq_detect IS
        PORT (
            CLK : IN STD_LOGIC;
            RST_N : IN STD_LOGIC;
            ENA : IN STD_LOGIC;
            DIN : IN STD_LOGIC;
            MATCH : OUT STD_LOGIC
        );
    END COMPONENT;

    TYPE state_type IS (ST_IDLE, ST_LOAD, ST_SHIFT, ST_MATCH, ST_DONE);
    SIGNAL state, next_state : state_type;
    attribute enum_encoding : string;
    -- specify FSM state encoding scheme: "one-hot", "sequential", "gray"
    attribute enum_encoding of state_type : type is "one-hot";

    SIGNAL shift_reg    : UNSIGNED(9 DOWNTO 0);
    SIGNAL shift_end    : STD_LOGIC;
    SIGNAL current_bit  : STD_LOGIC;
    SIGNAL match_flag   : STD_LOGIC;
    SIGNAL start_sync   : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '1');
    SIGNAL start_rising : STD_LOGIC;
    SIGNAL ena_fsm      : STD_LOGIC := '0';
    SIGNAL shift_cnt    : INTEGER RANGE 0 TO 10 := 0;

BEGIN
    -- Instance of the bit_seq_detect module
    detector_inst : bit_seq_detect
    PORT MAP(
        CLK   => CLK,
        RST_N => RST_N,
        ENA   => ena_fsm,
        DIN   => current_bit,
        MATCH => match_flag
    );

    -- START edge detector
    start_detect_proc : PROCESS (CLK, RST_N)
    BEGIN
        IF RST_N = '0' THEN
            start_sync <= (OTHERS => '1');
        ELSIF rising_edge(CLK) THEN
            start_sync <= start_sync(0) & START;
        END IF;
    END PROCESS;

    -- concurrent signal assignments
    start_rising <= NOT start_sync(1) AND start_sync(0);
    ena_fsm      <= '1' WHEN state = ST_SHIFT ELSE '0';
    shift_end    <= '1' WHEN shift_cnt = 9 ELSE '0';
    current_bit  <= shift_reg(9);

    -- Shift register process
    shift_reg_proc : PROCESS (CLK, RST_N)
    BEGIN
        IF RST_N = '0' THEN
            shift_reg <= (OTHERS => '0');
        ELSIF rising_edge(CLK) THEN
            IF state = ST_LOAD THEN
                shift_reg <= unsigned(SW); -- load the switch value
            ELSIF state = ST_SHIFT THEN -- shift left
                shift_reg <= shift_reg(8 DOWNTO 0) & '0';
            END IF;
        END IF;
    END PROCESS;

    shift_cnt_proc: PROCESS (CLK, RST_N)
    BEGIN
        IF RST_N = '0' THEN
            shift_cnt <= 0;
        ELSIF rising_edge(CLK) THEN
            IF state = ST_LOAD THEN
                shift_cnt <= 0;
            ELSIF state = ST_SHIFT THEN
                shift_cnt <= shift_cnt + 1;
            END IF;
        END IF;
    END PROCESS;

    -- FSM state register
    fsm_state_proc : PROCESS (CLK, RST_N)
    BEGIN
        IF RST_N = '0' THEN
            state <= ST_IDLE;
        ELSIF rising_edge(CLK) THEN
            state <= next_state;
        END IF;
    END PROCESS;

    -- FSM next-state logic
    next_state_proc : PROCESS (state, start_rising, match_flag, shift_end)
    BEGIN
        CASE state IS
            WHEN ST_IDLE =>
                IF start_rising = '1' THEN
                    next_state <= ST_LOAD;
                ELSE
                    next_state <= ST_IDLE;
                END IF;

            WHEN ST_LOAD =>
                next_state <= ST_SHIFT;

            WHEN ST_SHIFT =>
                IF match_flag = '1' THEN
                    next_state <= ST_MATCH;
                ELSIF shift_end = '1' THEN
                    next_state <= ST_DONE;
                ELSE
                    next_state <= ST_SHIFT;
                END IF;

            WHEN ST_MATCH =>
                next_state <= ST_IDLE;

            WHEN ST_DONE =>
                next_state <= ST_IDLE;

            WHEN OTHERS =>
                next_state <= ST_IDLE;
        END CASE;
    END PROCESS;

    leds_update_proc : PROCESS (CLK, RST_N)
    BEGIN
        IF RST_N = '0' THEN
            LEDS <= (OTHERS => '0');
        ELSIF rising_edge(CLK) THEN
            IF state = ST_SHIFT THEN
                LEDS(1) <= '0';
                LEDS(0) <= '0';
            ELSE
                IF state = ST_MATCH THEN
                    LEDS(1) <= '1';
                END IF;
                IF state = ST_DONE THEN
                    LEDS(0) <= '1';
                END IF;
            END IF;
        END IF;
    END PROCESS;

END rtl;

 

Figure: Example simulation waveforms for the bit sequence detector

Figure: FSM state encoding as shown in the State Machine Viewer

 

Post-Lab Questions for Lab 5#

  1. Is the FSM implementation in the VHDL code Moore-type or Mealy-type? Explain the key differences between Moore and Mealy FSMs.

  2. According to the FPGA compilation results, does the selected FSM state encoding (e.g., "sequential", "one-hot", or "gray code") impact FPGA resource usage, such as logic elements and flip-flops?

 

Lab 6: Parallel vs. Serial Parity Bit Calculation#

Objective:#

  • Learn how to implement parity bit calculation using two different approaches: serial computation and parallel computation.

Parity Bit Calculation#

Given an -bit data word stored in a register, the parity bit of the data word is computed as:

This is the bitwise XOR () of all bits in the data word.

Pseudo Code (Bit-Serial Computation)

p = 0
for i in 0 to N-1 loop
    p = p xor b[i]
return p

 

Lab Procedure:#

  1. Write VHDL code that implements the parity calculation.

    • The design entity (bit_parity_calc) should have the following I/O interface:
      • CLK clock input
      • RST_N asynchronous reset (active-low) input
      • DATA[N-1..0] n-bit data input, (N is a VHDL generic)
      • START start input
      • DONE done status output
      • PARITY parity bit output
    • Functional Description:
      • The module should compute the parity bit when START is asserted, assert DONE when the result is ready, and output the computed parity on PARITY.

  2. Implement the bit_parity_calc module using two different approaches:

    • Bit-parallel computation:
      • Use a combinational XOR tree to compute the parity in one cycle.
    • Bit-serial computation:
      • Use sequential logic to XOR one bit at a time over multiple clock cycles (e.g., using a shift register and accumulator).
    • Notes:
      • In the bit-parallel design, all bits are XORed in a combinational logic tree.
      • In the bit-serial design, bits are XORed one at a time over multiple clock cycles.

  3. Write a VHDL testbench for simulation to verify the correctness of both implementations.

    • Capture the simulation waveforms for inclusion in the lab report.

  4. Synthesize and Test the Design on FPGA using Quartus Prime Lite.

    • Create a Quartus Prime Lite project and compile the VHDL design.
    • Upload the synthesized design to your FPGA development board.
    • Hardware Setup:
      • Use 10-bit slide switches as data input: DATA[9..0]
      • Use two push buttons for control signals: RST_N and START
      • Use two LEDs for the DONE and PARTITY output.
    • Capture the schematic of synthesized circuit as shown in RTL Viewer for inclusion in the lab report.
    • Demonstrate your design to the lab instructor for validation.

Post-Lab Questions for Lab 6#

  1. Compare the bit-serial and bit-parallel implementations in terms of execution time (latency) and hardware resource usage.

  2. How does increasing the value of N affect each design implementation?

  3. In the bit-serial implementation, how many clock cycles are required from START to DONE?

 

Lab 7: RGB Color Sequencing#

Objective:#

  • Learn how to write VHDL code to implement a bit pattern sequencer to drive an RGB LED.

Lab Procedure#

  1. Write VHDL code to implement a bit-pattern sequencer that generates a 3-bit control signal to drive an RGB LED module, as specified by the following sequence:

    • RGB: 000 -> 001 -> 010 -> 011 -> ... -> 110 -> 111

  2. The entity of the bit-pattern sequencer (rgb_sequencer) has the following I/O interface:

    • CLK: clock input (50 MHz)
    • RST_N: asynchronous reset (active-low) input
    • SW[1:0]: speed selection input
    • RGB[2:0]: RGB output

  3. The two slide switches are used as inputs to select the sequence speed as specified in table below.

  4. Create a VHDL testbench to simulate the design and verify functional correctness.

  5. Use higher values for the speed settings (for Fast, Moderate and Slow) to reduce the simulation time.

  6. Capture the simulation waveforms for inclusion in the lab report.

  7. Create a Quartus Prime project, apply correct FPGA pin assignments,
    compile the VHDL source code, and upload the bitstream to the FPGA board to test the design.

SW[1:0] Speed
00 Paused
01 Fast (10 Hz)
10 Moderate (5 Hz)
11 Slow (1 Hz)

Table: Speed selection

 

Figure: Examples of RGB modules (both CA and CC types)

Figure Sample simulation waveforms

Figure The MAX10 Lite FPGA board with an RGB module (CA)

 

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Created: 2025-06-08 | Last Updated: 2025-06-15