Lab Sheet 1#

This lab sheet contains the following lab activities:

• Lab 1: Measuring Electrical & Timing Parameters of Discrete Logic Gates
• Lab 2: Creating a 2-to-1 MUX Using NAND Logic Gates
• Lab 3: Creating an RS Latch Using NAND Logic Gates
• Lab 4: Building an Edge Detector with Pulse Generator using NAND Gates or 555 Timer IC
• Lab 5: Schmitt-Trigger Input

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Lab 1: Measuring Electrical & Timing Parameters of Discrete Logic Gates#

Components Required#

• Logic gate IC: 74HC00 (Quad 2-input NAND gate)
• Resistors (1kΩ and 200Ω)
• Capacitors (10nF and 100nF)
• Breadboard, jumper wires
• DC power supply
• Digital multimeter (DMM)
• Digital oscilloscope
• Function generator
• USB flash drive (for saving waveform data)

Lab Procedure#

1. Hardware Implementation: Implement a NOT gate using a 74HCT00N IC on a breadboard.

   • Connect all unused input pins (if any) to GND (do not leave them floating).

2. Power Connection: Connect +5Vdc and GND from the power supply to the VCC and GND pins of the 74HC00N IC, respectively.

3. Test Signal Generation: Use a function generator to generate rectangular wave (i.e. a digital pulse signal) with the following settings as the input signal of the NOT gate:

   • Peak-to-Peak Voltage (V_pp): 5V
   • DC Offset (V_offset): 2.5V
   • Frequency: 10kHz or 100kHz
   • Note: Ensure that V_min (LOW) = 0V and V_max (HIGH) = 5V

4. Signal Measurement: Use a digital oscilloscope to measure, analyze, and capture the input waveform to verify correct settings before applying the signal to the input pin.

   • Use two probes of a digital oscilloscope on CH1 and CH2 to measure the input and output signals of the NOT gate, respectively.

5. Waveform Analysis & Parameter Measurement: Use the digital oscilloscope to measure the following parameters:

   • Rise time and fall time of the output signal:
     • Rising from 10% to 90% of VCC: t_r or t_TLH
     • Falling from 90% to 10% of VCC: t_f or t_THL
   • Propagation delays:
     • t_PHL (HIGH-to-LOW delay)
     • t_PLH (LOW-to-HIGH delay)
     • Average propagation delay: t_pd = (t_PHL + t_PLH) / 2
   • Voltage level of HIGH logic output
   • Voltage level of LOW logic output
   • Note:
     • Adjust the time/div setting of the oscilloscope to achieve appropriate time resolution for accurate measurement.
     • Capture the waveforms and save them as .PNG files on a USB flash drive, for inclusion in the lab report.

6. Floating Input: Leave the input of the NOT gate unconnected (floating). Measure the signal at the output pin.

   • Do not connect a probe to the input pin of the NOT gate.
   • Observe and capture the output waveform using the oscilloscope.

7. Input Voltage Test: Change the parameters of the input signal:

   • (V_min,V_max): (0V,5V) → (0.5V,4.5V) and (1.0V,4.0V), respectively.
   • Observe and capture the output waveform on the oscilloscope for each case.

8. Capacitive Load Test: Add a capacitive load (C_L) to the output pin of the NOT gate:

   • Use the input signal as defined in Step 3.
   • Use different values for C_L, such as 10nF and 100nF.
   • Observe and capture the output waveform on the oscilloscope for each case.

9. Resistive Load Test: Add a resistive load (R_L) to the output pin of the NOT gate.

   • Use the input signal as defined in Step 3.
   • Use different values for R_L, such as 1kΩ and 200Ω.
   • Observe and capture the output waveform on the oscilloscope for each case.

10. Output Indication: Modify the circuit on the breadboard by adding two LEDs (each with a 1kΩ current-limiting resistor) such that the LEDs blink alternately in response to a pulse signal (Frequency = 10Hz) applied to the NOT gate.

    • Take a photo of your breadboard circuit for inclusion in the lab report.

Figure: Test setup for measuring timing parameters using a 74HC00 logic gate. In this case, all NAND2 gates are configured as inverters. One inverter drives three additional inverters to demonstrate a fan-out greater than 1.

Figure: 74HC/HCT00 Pinout, PDIP-14 IC Package

Figure: 74HC/HCT00 Timing Parameters - Propagation Delays, Transition Times, Rise and Fall Times (Source: Nexperia)

Figure: Sample Waveform (CH1: Input Signal, CH2: Output Signal)

Figure: Rise & Fall Time Measurement (using the cursor function of the digital oscilloscope)

74HC/HCT00N Datasheets (from different manufacturers)#

• TI: SN74HC00, SN74HCT00
• Nexperia/Wingtech:: 74HC/HCT00
• Diodes: 74HC00, 74HCT00

 

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Post-Lab Questions for Lab 1#

1. What are the measured values for the following parameters? Compare each measured value with the corresponding value specified in the datasheet.

   • Transition time (t_t): t_pd = (t_PLH + t_PHL) / 2
   • Propagation delay (t_d): t_t = (t_TLH + t_THL) / 2

2. According to the manufacturer's datasheet for 74HCT00N, what are the typical values of the following parameters at room temperature (25°C):

   • V_IL (Input Low Voltage)
   • V_IH (Input High Voltage)
   • V_OL (Output Low Voltage)
   • V_OH (Output High Voltage)

3. What would happen if the input voltage is VCC/2 = 2.5V? Why must this condition be avoided?

4. How does the capacitive load (C_L) affect the rise time, fall time, and propagation delay? Explain why these effects occur.

5. When reducing the input voltage swing (e.g., from 0V–5V to 1V–4V), how does the output waveform behavior change?

6. What are the potential effects of leaving unused inputs floating on a CMOS logic IC like the 74HC/HCT00? Why is it important to tie unused inputs to a defined logic level?

7. As the resistive load decreases (i.e., causing more current to flow), how does the output waveform behavior change? Explain why this happens in terms of the drive capability of the gate.

8. Does decreasing the load resistor cause an increase in source current? Explain why.

9. What are the key differences between the 74HCTxx and 74HC00xx logic families?

10. Can both the 74HCxx and 74HCTxx operate correctly with V_CC = +3.3V?

 

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Lab 2: Creating a 2-to-1 MUX Using NAND Gates#

Components Required#

• Logic gate IC: 74HC00 (Quad 2-input NAND gate)
• Slide switch (SPDT)
• Capacitor (10nF)
• Breadboard, jumper wires
• DC power supply
• Digital multimeter (DMM)
• Digital oscilloscope
• Function generator

Lab Procedure#

1. Pre-Lab Simulation: Model a 2-to-1 multiplexer (MUX) using a 74HC/HCT00 IC (quad two-input NAND gates). Create and simulate a virtual circuit prototype on a breadboard.

   • Select input: S
   • Data inputs: A and B
   • Data output: O = A · /S + B · S (where /S is the logical NOT of S)
   • Note: This task must be completed before the lab session.

2. Hardware Implementation: Implement the 2-to-1 MUX circuit using the 74HCT00N IC on a physical breadboard.

   • Use a slide switch (SPDT - Single Pole Double Throw) to select either VCC or GND as the select input (S) of the MUX.
   • Connect the input A to GND.
   • Apply a pulse signal from a function generator to the input B of the MUX.
     • Peak-to-Peak Voltage (V_pp): 3V
     • DC Offset (V_offset): 1.5V (V_min = 0V and V_max = 3V)
     • Frequency: 10kHz or 100kHz
   • Add a capacitor (e.g. 10nF) between the input S and GND.

3. Power Connection: Connect +5V DC and GND from the power supply to the V_CC and GND pins of the 74HCT00N IC, respectively.

4. Circuit Testing and Verification: Test the function of the MUX circuit by changing the position of the slide switch.

   • Use a 4-channel digital oscilloscope to measure the inputs B and S and the output O, using channels CH1, CH2 and CH3, respectively.
   • Capture the waveform to detect the transition 0 -> 1 and then 1 -> 0 on the S signal.
   • Verify the input/output logic levels against the truth table of a 2-to-1 MUX.

Figure: Schematic of a NAND2-based 2-to-1 MUX circuit (drawn with EasyEDA)

Figure: Measurement of MUX's signals (CH1 = B, CH2 = O and CH3= S)

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Post-Lab Questions for Lab 2#

1. Explain how the Boolean expression O = (A · /S) + (B · S) is implemented using only 2-input NAND gates. Detail the logic for each stage of your NAND gate implementation.

2. Based on the captured waveforms for the transitions on S, describe how the output waveform changed relative to the input waveforms (A and B).

3. If the input A of the 2-to-1 MUX is connected to GND, what is the equivalent Boolean expression for the output of the MUX? How can this function be reimplemented using only 2-input NAND gates? Draw the schematic of your circuit.

 

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Lab 3: Creating an RS Latch Using NAND Gates#

Components Required#

• Logic gate IC: 74HC00 (Quad 2-input NAND gate)
• Push buttons
• Slide switch
• LEDs + current-limiting resistors
• Breadboard, jumper wires
• DC power supply
• Digital multimeter (DMM)
• Digital oscilloscope

Lab Procedure#

1. Pre-Lab Simulation: Model an RS latch using a 74HC/HCT00 IC. Create and simulate a virtual circuit prototype on a breadboard.

   • Inputs: /S (active-low set) and /R (active-low reset)
   • Data outputs: Q (non-inverting output) and /Q (inverting output)
   • Hint: Use two 2-input NAND gates connected in a cross-coupled configuration to implement the RS latch..
   • Note: This task must be completed before the lab session.

2. Hardware Implementation (RS Latch): Implement the RS latch using the 74HCT00N IC on a breadboard.

   • Use two active-low push-button switches (referred to as SW1 and SW2) with pull-up resistors (e.g., 10kΩ) for the /S and /R inputs of the RS latch.

3. Output Indication: Connect two LEDs, each with a current-limiting resistor, to the output pins of the RS latch.

   • The LED will illuminate (ON) when the corresponding output logic level is HIGH.

4. Power Connection: Connect +5V DC and GND from the power supply to the V_CC and GND pins of the 74HC00N IC, respectively.

5. Circuit Testing and Verification (RS Latch): Test the RS latch with all possible input combinations to verify functional correctness.

   • Press the push buttons to test the circuit. Use the test cases for the inputs /S and /R as specified by the table below.
   • Use a digital multimeter (DMM) to measure the voltages of the inputs and outputs.
   • Turn the power supply off and on again, and observe the initial states of both LEDs.
   • Take a photo of your breadboard circuit for inclusion in the lab report.

6. RS Latch for Slide-Switch Debouncing: Modify the RS latch circuit as follows.

   • Remove the switches SW1 and SW2.
   • Use a slide switch with:
     • Center pin connected to GND
     • Outer pins connected to VCC through pull-up resistors
   • Connect one outer pin of the slide switch to /S and the other outer pin to /R.
   • Rapidly change the slide-switch position and use an oscilloscope to monitor inputs /S, /R and the output Q of the RS latch.
   • Observe and capture the waveforms of /S, /R and Q using the oscilloscope.

7. Hardware Implementation (Gated RS Latch): Modify the RS latch to implement a gated RS latch:

   • The gated RS latch has the following I/Os:
     • Inputs: S (active-high set), R (active-high reset) and EN (enable or clock input)
     • Outputs: Q (non-inverting output) and /Q (inverting output)
   • The push-button switches SW1 and SW2 should be active-high (with pull-down resistors).
   • Use a slide switch to provide the logic HIGH or LOW for the input EN.

8. Circuit Testing and Verification (Gated RS Latch):

   • Take a photo of your breadboard circuit for inclusion in the lab report.

Table: The truth table for an RS latch with active-low inputs

/R (Reset)	/S (Set)	Q	/Q	Description
HIGH	HIGH	Q	/Q	Hold (no change)
LOW	HIGH	0	1	Reset state
HIGH	LOW	1	0	Set state
LOW	LOW	X	X	Invalid state

 

Simulation Demo#

Figure: Schematic of a NAND2-based RS latch circuit (drawn with EasyEDA in Simulation mode)

Figure: Schematic of a NAND2-based RS latch circuit for slide-switch debouncing (drawn with EasyEDA in Simulation mode)

Figure: Schematic of a gated NAND2-based RS latch circuit (drawn with EasyEDA in Simulation mode)

Figure: Virtual circuit simulation of a RS Latch (with AUTODESK Tinkercad)

Figure: Virtual circuit simulation of a RS Latch for Slide Switch Debouncing

 

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Post-Lab Questions for Lab 3#

1. Explain the "forbidden state" for an RS latch built with NAND gates. What happens to the outputs when both /S and /R are simultaneously asserted (LOW) or when both push-buttons are held pressed?

2. What happened to the output Q and /Q when the EN input of the gated RS latch is LOW (de-asserted), regardless of changes in any input?

3. What are the initial states of Q, /Q, and both LEDs after a power reset?

4. Explain how an RS latch can be used to de-bounce a slide switch.

5. Based on the observed waveforms, is it possible for both /S and /R of the RS latch to be LOW at the same time when using slide switches as input controls?

6. Explain how to implement a D latch based on a RS latch. Draw a schematic diagram of the D latch implementation using 2-input NAND gates only.

 

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Lab 4: Building an Edge Detector with Pulse Generator using NAND Gates or 555 Timer IC#

Components Required#

• Logic gate IC: 74HC00 (Quad 2-input NAND gate)
• 555 Timer IC
• Resistors and capacitors
• Push button
• Potentiometer
• Breadboard, jumper wires
• DC power supply
• Digital oscilloscope
• Function generator

Lab Procedure#

1. Pre-Lab Simulation: Model a digital circuit using a 74HC/HCT00 IC to detect a rising edge on a pulse signal. Create and simulate a virtual circuit prototype on a breadboard.

   • Key Idea: A short pulse is generated when: O = D AND (NOT D_delayed), where D is the input, D_delayed is its time-delayed (RC-delayed) version of D and O is the output.
   • Expected Result:
     • When the input goes from LOW → HIGH, the output O generates a short HIGH pulse.
     • The HIGH pulse width must be between 0.1 msec and 1 msec.
   • Note: This task must be completed before the lab session.

2. Hardware Implementation (NAND-based edge detector): Implement the circuit using the 74HCT00N IC on a breadboard.

   • Use a push button with a pull-up resistor (e.g., 10kΩ) to connect the input D of the circuit.
   • Use VCC = 5V as the supply voltage.

3. Circuit Testing and Verification (NAND-based edge detector): Test the circuit.

   • Try pressing and quickly releasing the push button to generate a very short active-low pulse.
   • Use a digital oscilloscope to monitor both input and output signals.

4. Using a 555 Timer IC in Monostable Mode: Build a circuit on the breadboard to generate a single short pulse when a push button is clicked and then released. The HIGH pulse width of the output should be between 5 msec to 50 msec.

   • Draw the schematic of the circuit.
   • Take a photo of the implemented circuit that works correctly as expected.

5. Circuit Testing and Verification (555 Timer-Based Edge Detector): Test the circuit.

   • Use a digital oscilloscope to analyze the input and output waveforms.
   • Try pressing and quickly releasing the push button to generate a very short active-low pulse.
   • Compare the results with those of the NAND2-based circuit.
   • Discuss the differences in how each circuit detects or responds to trigger conditions.
   • Use a function generator to produce a PWM (Pulse Width Modulation) signal to test the circuit, ensuring that the output is also a periodic signal. Select the frequency and pulse width of the input signal appropriately. Capture both the input and output waveforms.

Datasheet for 555 Timer ICs#

• TI: LM555, NE555
• Diodes: NE555

Simulation Demo#

Figure: Schematic of a pulse detector using NAND2 gates with a RC delay circuit

Figure: Virtual circuit simulation using a function generator to produce a periodic pulse signal and an oscilloscope to measure the output signal.

Figure: Virtual circuit simulation of a 555 timer-based circuit that detects a falling edge transition triggered by a push button press and generates a pulse as output.

 

Signal Measurement Demo#

Figure: Sample waveforms from a 555 Timer IC circuit, measured using an oscilloscope (CH1 = Input or Trigger signal, CH2 = Output pulse signal).

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Post-Lab Questions for Lab 4#

1. How does the value of the RC time constant affect the pulse width of the output?
2. Compare the simulation result with the actual oscilloscope waveform. Are they consistent? If not, why?
3. How would you modify the circuit to detect a falling edge instead of a rising edge?
4. In a 555 Timer monostable circuit, what condition on the input signal initiates pulse generation?
5. How can the pulse width of the output signal of a 555 Timer circuit be made adjustable using a potentiometer? Draw the modified 555 Timer based circuit.
6. What is the 74HC/HCT132? Can it be used in place of the 74HCT00N? Are there any advantages?

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Lab 5: Schmitt-Trigger Input#

Components Required#

• Logic gate IC: 74HCT14N (Hex Schmitt-Trigger Inverters)
• Breadboard, jumper wires
• DC power supply
• Digital oscilloscope
• Function generator

Lab Procedure#

• Hardware Implementation:
  • Select one NOT gate inside the 74HCT14N as DUT (Device Under Test).
  • Use +5Vdc as the supply voltage for the IC.
• Circuit Testing and Verification: Use a triangular input signal.
  • V_offset: 2.5V
  • Peak-to-Peak Voltage (V_pp): starting from 2.5V, up to 4.0V
  • Frequency: 10kHz
• Signal Measurement: Use a digital oscilloscope to measure signals.
  • Probe Channels: CH1 = Input signal, CH2 = Output signal
  • Volt/Div Setting Use 1V/div and also ground reference level for both channels. Adjust the vertical alignment of both waveforms properly.
  • Use cursor function to measure the following parameters:
    • The largest voltage level of the input signal that causes the HIGH → LOW transition on the output.
    • The smallest voltage level of the input signal that causes the LOW → HIGH transition on the output.

Datasheet for 74HC/HCT14 ICs#

• TI: SN74HCT14
• Nexperia: 74HC/HCT14
• Diodes:: 74HCT14

 

Simulation Demo#

Figure: Simulation of a non-inverting Schmitt-trigger buffer with 74HC14N (hex Schmitt-trigger inverters) using AUTODESK Tinkercad

Figure: Simulation waveforms of input and output signals

 

Figure: Simulation of two cascaded inverting Schmitt-trigger buffer using EasyEDA

 

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Post-Lab Questions for Lab 5#

1. According to the experiment, what happens when increasing the V_pp of the triangular test signal? What type of waveform is the output?

2. Explain the definition of V_T+ (Positive-going threshold), V_T– (Negative-going threshold), and the hysteresis of a Schmitt-Trigger input.

3. What are typical values for V_T+ and V_T– given in the datasheet?

4. How to use a digital function generator to generate the following test signal?

Figure: Test signal generated using a digital function generator

 

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Created: 2025-05-22 | Last Updated: 2025-06-15