Tutorial: Clock Generation Using ALTPLL IP Core#

On-Chip IP Core for Clock Generation#

In order to work with a slower clock or an operating rate than the system input clock to the FPGA device, there are three main approaches:

Clock Divider Approach: Implement a clock frequency divider to generate a slower clock signal and use it to trigger the counter.
PLL Approach: Use an on-chip clock generation and management block such as PLL (Phase-Locked Loop) to generate a slower clock signal and use it to trigger the counter.
Clock Enable Approach: Generate a single-cycle, periodic enable signal that occurs at a lower rate and use it to enable the counter increment.

A PLL is a closed-loop circuit used for frequency control. It compares the phase of an input signal with the output of a voltage-controlled oscillator (VCO). Through negative feedback, the PLL adjusts the VCO to align the output signal's phase with that of the input, achieving phase lock.

Intel/Altera FPGA devices, such as Cyclone V and MAX 10, include on-chip clock generation and management units like PLLs:

These PLLs are hard IP cores. For MAX10 devices, up to four PLLs are available.
They can take an external clock input (e.g., from an oscillator) and generate multiple derived clock signals with higher or lower frequencies.
They also support programmable phase shifts and duty cycle adjustments.

A clock output of a PLL block is typically used as a clock signal (not as a data signal) to trigger the operation of synchronous logic in a digital design (e.g. connecting to the clock input pin of D-type flip flops).

The ALTPLL megafunction is available in the IP Catalog of the Quartus Prime Lite software. ALTPLL IP configuration options include:

Parameter Settings:
- Modes:
  - Normal: General-purpose use (default).
  - Source Synchronous: This aligns clocks for high-speed interfaces.
  - Zero Delay Buffer (ZDB): This minimizes delay between input and feedback clock.
- Inputs: Select the input clock source(s).
- Locked Output:
  - This enables a status output signal (locked) that indicates whether the PLL has achieved phase and frequency lock. It goes HIGH once the PLL output is stable and can be used to enable downstream logic.
- Bandwidth: Choose between Low (better jitter rejection) or High (faster lock time).
- Clock Switch-Over:
  - This allows the PLL to switch between multiple clock inputs for redundancy or failover.
PLL Dynamic Reconfiguration:
- This enables modification of certain PLL parameters (e.g., output frequencies or phases) at runtime.
Output Clocks:
- This specifies how many clock outputs the PLL will generate (e.g., c0, c1, etc.). Each can have independent frequency, phase, and duty cycle settings.

For PLL clock output generation, the output clock frequency can be either higher or lower than the input clock frequency. This depends on parameters such as the multiplication factor and the division factor.

The general formula for PLL clock output frequency is as follows:

$f_{out} = f_{in} \times \frac{M}{N},$ where:

$f_{in}$ = Input clock frequency (from external source or on-chip oscillator)
$M$ = Multiplication factor
$N$ = Division factor

For example, to generate 1MHz output clock from a 50MHz input clock, the multiplication and division factors are set to $M=1$ and $N=50$ , respectively.

A clock output of a PLL block is typically used as a clock signal (not as a data signal) to trigger the operation of synchronous logic in a digital design—for example, by connecting it to the clock input of D-type flip-flops or registers.

ALTPLL Configuration Demo#

The steps to configure and generate an ALTPLL IP core using MegaWizard Plug-in Manager are shown below.

Navigate to IP Catalog > Library > Basic Functions > Clocks, PLLs, and Resets > PLL.
Double-click ALTPLL to launch the configuration wizard.
Specify a component name for the ALTPLL instance and select VHDL as the output HDL.
Use the default PLL type (Normal mode with internal feedback).
Enter the input clock frequency (e.g., 50 MHz).
Enable the areset input (asynchronous, active-high reset signal for the PLL).
Enable the locked output (indicates when PLL is locked to the input clock).
Set Bandwidth to Auto.
Disable Clock Switch-Over.
Disable Dynamic PLL Reconfiguration.
Configure the desired clock outputs (c0 to c4) with specific frequencies and phases.
Complete the wizard and generate the output files.

Figure: Quartus Prime Lite + IP Catalog tab

Figure: Setting the IP variation name and selecting the output language (VHDL)

Figure: ALTPLL parameter configuration - input clock frequency, PLL type, and PLL operation mode

Figure: ALTPLL parameter configuration - asynchronous reset input, and locked output for PLL

Figure: ALTPLL parameter configuration - bandwidth (auto)

Figure: ALTPLL parameter configuration - clock input switch-over (disabled)

Figure: ALTPLL parameter configuration - PLL dynamic reconfiguration (disabled)

Figure: ALTPLL output clock c0 (frequency 1MHz, duty cycle 50% and phase shift 0°)

Figure: ALTPLL output clock c1 (frequency 1MHz, duty cycle 50% and phase shift 180° or inverted)

Figure: ALTPLL output clock c2 ~ c4 (disabled)

Figure: Selecting the simulation library (alt_mf)

Figure: ALPLL output file generation

Figure: Insertion of the qip (Quartus Prime IP) file to the project

VHDL Instantiation & Demo Code#

The following VHDL code shows how to instantiate the previously generated ALTPLL IP core and use it as a component named clk_gen.

The ALTPLL component receives a 50MHz input clock and generates two output clocks, c0 and c1, of the same frequency but with complementary (inverted) phases.

The top-level design (clkpll_demo) instantiates an ALTPLL component named clk_gen. The locked output pin of the component is unused and left unconnected (open). The areset input pin of the component is driven by the inverted signal from the RST_N pin (an active-low push-button).

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY clkpll_demo IS
    PORT (
        CLK_50MHZ  : IN STD_LOGIC;
        RST_N      : IN STD_LOGIC;
        CLK_O      : OUT STD_LOGIC;
        CLK_O_INV  : OUT STD_LOGIC
    );
END clkpll_demo;

ARCHITECTURE rtl OF clkpll_demo IS

    COMPONENT clk_gen IS
        PORT (
            areset : IN STD_LOGIC := '0';
            inclk0 : IN STD_LOGIC := '0';
            c0     : OUT STD_LOGIC;
            c1     : OUT STD_LOGIC;
            locked : OUT STD_LOGIC
        );
    END COMPONENT;

    SIGNAL areset : STD_LOGIC := '1';

BEGIN

    areset <= NOT RST_N;

    CLK_GEN_inst : clk_gen PORT MAP(
        areset => areset,
        inclk0 => CLK_50MHZ,
        c0     => CLK_O,
        c1     => CLK_O_INV,
        locked => OPEN
    );

END ARCHITECTURE;

The following is the Tcl script for pin assignments targeting the DE10-Lite FPGA board. The output signals (CLK_O and CLK_O_INV) are routed to the I/O pins at the locations PIN_AB21 and PIN_AA20 (Arduino shield pins IO14 and IO15, respectively).

# File: assignments.tcl
#============================================================
# CLOCK (MAX10_CLK1_50)
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_50MHZ
set_location_assignment PIN_P11 -to CLK_50MHZ

#============================================================
# Push Buttons (KEY)
#============================================================

set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to RST_N
set_location_assignment PIN_B8 -to RST_N

#============================================================
# Arduino I/O 14 & 15 
#============================================================

set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_O
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_O_INV
set_location_assignment PIN_AB21 -to CLK_O
set_location_assignment PIN_AA20 -to CLK_O_INV

#============================================================

Example of Synopsys Design Constraints File (.sdc) that can be used for static timing analysis (STA) of the design:

# Main system clock (50 MHz -> 20ns period)
create_clock -name "CLK_50MHZ" -period 20.000 [get_ports {CLK_50MHZ}]

# Automatically derive generated clocks (e.g., PLL outputs)
derive_pll_clocks -create_base_clocks

# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

Figure: Output pin locations and signal measurement using a digital oscilloscope

Figure: Two complementary clock output Waveforms (1MHz output)

Cascaded ALTPLL Components#

In this section, the ALTPLL IP component is reconfigured to generate two complementary output clocks with a frequency reduction ratio of 1:1000.

Figure: Clock output settings (c0) using a multiplication factor of 1 and a division factor of 1000

Figure: Clock output settings (c1) using a multiplication factor of 1 and a division factor of 1000, but with a phase shift of 180°

The following VHDL code demonstrates how to instantiate two ALTPLL components in a cascaded configuration to further reduce the output clock frequency. The clock output of the first ALTPLL is connected to the clock input of the second ALTPLL. Additionally, the inverted locked output of the first ALTPLL is used as the asynchronous reset (areset) input of the second ALTPLL.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY clkpll_demo IS
    PORT (
        CLK_50MHZ  : IN STD_LOGIC;
        RST_N      : IN STD_LOGIC;
        CLK_O      : OUT STD_LOGIC;
        CLK_O_INV  : OUT STD_LOGIC
    );
END clkpll_demo;

ARCHITECTURE rtl OF clkpll_demo IS

    COMPONENT clk_gen IS
        PORT (
            areset : IN STD_LOGIC := '0';
            inclk0 : IN STD_LOGIC := '0';
            c0     : OUT STD_LOGIC;
            c1     : OUT STD_LOGIC;
            locked : OUT STD_LOGIC
        );
    END COMPONENT;

    SIGNAL areset1     : STD_LOGIC := '1';
    SIGNAL areset2     : STD_LOGIC := '1';
    SIGNAL slower_clk  : STD_LOGIC := '0';
    SIGNAL locked      : STD_LOGIC := '0';

BEGIN

    areset1 <= NOT RST_N;

    CLK_GEN_inst1 : clk_gen PORT MAP(
        areset => areset1,
        inclk0 => CLK_50MHZ,
        c0     => slower_clk,
        c1     => OPEN,
        locked => locked
    );

    areset2 <= areset1 AND (NOT locked);

    CLK_GEN_inst2 : clk_gen PORT MAP(
        areset => areset2,
        inclk0 => slower_clk,
        c0     => CLK_O,
        c1     => CLK_O_INV,
        locked => OPEN
    );

END ARCHITECTURE;

Figure: Two complementary clock output Waveforms (50Hz output)

According to the waveforms, the output clock frequency is 50 Hz, derived from a 50 MHz input clock using a reduction factor of $1 / (1000 \times 1000)$ .

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Created: 2025-05-31 | Last Updated: 2025-05-31

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